Instruction Cache
Not just the data used by the processor is cached;
the instructions executed by the processor are also cached.
However, this cache is much less problematic(问题) than the data ca...
Other Details
So far we talked about the address as consisting of threeparts, tag, set index, and cache line offset.
But what address is actually used? All relevant processors today provide virtu...
Special Case: Hyper-Threads
Hyper-Threads (sometimes called Symmetric Multi-Threading(对称多线程), SMT) are implemented by the CPU and are a special case since the individual threads(单个线程) cannot reall...
Multi Threaded Access
Multi Threaded Access To ensure that the gravity(重力) of the problems introduced by concurrently using the same cache lines on different processors is understood, we will look...
回顾
In the previous section we have already pointed out the problem we have when multiple processors come into play.
Even multi-core processors have the problem for those cache levels which are no...
Write Behavior
Before we start looking at the cache behavior when multiple execution contexts (threads or processes) use the same memory we have to explore a detail of cache implementations.
Cach...
Measurements of Cache Effects
All the figures are created by measuring a program which can simulate working sets of arbitrary(随意) size,
read and write access, and sequential or random access.
We...
CPU Cache Implementation Details
Cache implementers have the problem that each cell in the huge main memory potentially(可能) has to be cached.
If the working set of a program is large enough this ...